The present invention generally relates to semiconductor devices, and more particularly to a static random access memory that uses a thin film transistor (TFT) for improved integration density.
The static random access memory (SRAM) is a random access memory that stores information by the latching operation of a flip-flop circuit. The device does not require periodical refreshing contrary to the dynamic random access memory (DRAM), and is suitable for a memory that is required to have a high speed access. For example, the SRAM is used extensively for the cache memory of computers. On the other hand, SRAMs have a problem in the integration density, as they use a flip-flop circuit that includes a number of transistors, for the memory cells.
FIG. 1 shows the circuit diagram of a typical SRAM that uses transistors 2, 3, 9 and 10 that form a flip-flop circuit 8. There, the transistors 2 and 3 are formed of an n-channel MOS transistor while the transistors 9 and 10 are formed of a p-channel MOS transistor. Further, transfer gate transistors 6 and 7 are provided in correspondence to complementary bit lines BL and /BL as usual, wherein the transistors 6 and 7 are activated by a word enable signal on a word line WL.
In the construction of FIG. 1, it should be noted that all the transistors 2, 3, 6, 7, 9 and 10 are formed of so-called bulk transistors that have a channel region as well as source and drain regions formed in a single crystal substrate of a semiconductor material such as silicon. In other words, the are disposed on a planar surface of the substrate with an isolation region formed between the transistors. Typically, the isolation region has a size of a few microns. Thus, the SRAM of FIG. 1 has suffered from a problem of low integration density as compared with the DRAMs.
In order to improve the integration density of conventional SRAMs, a construction as shown in FIG. 2 is proposed. There, p-channel MOS transistors 4 and 5 that form a flip-flop circuit 1 together with the n-channel MOS transistors 2 and 3, are replaced by polysilicon resistors 4 and 5 that are provided at a level above the transistors 2 and 3. This prior art device, however, has a problem of increased power consumption as the current flows continuously through the flip-flop circuit 8.
FIG. 3 shows a circuit diagram of another prior art SRAM that uses a flip-flop circuit 11, wherein the resistors 4 and 5 of the circuit of FIG. 2 are replaced by p-channel thin film transistors (TFT) 12 and 13. The p-channel TFT is a transistor that has a channel region comprised of a polysilicon strip. There, the polysilicon strip is doped to the p-type in correspondence to the source and drain regions except for a channel region that is formed as an undoped region located between the source and drain regions. Further, a gate electrode is provided above the channel region with an intervening insulation layer. It will be noted that such a TFT, formed on a polysilicon strip, does not need the substrate and can be provided easily into a multi-level configuration. Thereby, one can increase the integration density of the SRAM significantly.
FIG. 4 shows a circuit diagram that improves the integration density of the circuit of FIG. 3 further.
Referring to FIG. 4, it will be noted that the SRAM uses a flip-flop circuit 14 that in turn includes n-channel TFTs 15 and 16 in place of the transistors 2 and 3 of the flip-flop circuit 11 of FIG. 3. The n-channel TFT uses a polysilicon strip for the channel region similarly to the p-channel TFT except that the polysilicon strip is doped to the n-type in correspondence to the source and drain regions. Further, the transfer gate transistors 6 and 7 are also replaced by n-channel TFTs 17 and 18, respectively. By constructing the flip-flop circuit 14 as well as the transfer gate transistors 17 and 19 entirely from the TFT, one can increase the integration density further.
On the other hand, the device of FIG. 4 has a drawback, associated with the characteristic of the currently available TFT, in that it takes a relatively long time for changing the voltage level of the bit lines BL and /BL when reading or writing data. It should be noted that the bit lines BL and /BL have a relatively large parasitic capacitance. On the other hand, currently available TFTs can provide only a limited turn-on current as compared with the bulk transistors used in the conventional SRAMs. In a typical example, a TFT transistor shows the turn-on current of about 10 .mu.A, while a typical bulk MOS transistor shows the turn-on current of 1-2 mA. Obviously, this reduced turn-on current is caused by the scattering of carriers at the grain boundary of polysilicon. Thereby, the time needed for discharging the parasitic capacitance of the bit lines becomes inevitably longer, and the operational speed of the SRAM is slowed down as a result.